Simulation VIP for Ethernet Base-T1

Overview

Mature and highly capable compliance verification solution.

ncorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet Base-T1 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, the VIP for Base-T1 Ethernet helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Base-T1 Ethernet runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

The VIP for Base-T1 Ethernet enables verification of Ethernet interfaces in standalone, partial-stack, and full-stack mode for speeds of 10Mbps, 100Mbps, and 1000Mbps:

Supported specifications: IEEE specifications of 802.3bw-2015, 802.3bp-2016, and 802.3cg-2019.

Key Features

  • 10 Base-T1s Interface
    • Based on IEEE 802.3cg-2019 (Clause 147)
      • 4b/5b Encoder/Decoder
      • 17bit self-synchronizing scrambler/descrambler
      • PCS Transmit FSM
      • PCS Receive FSM
      • Differential Manchester Encoding (DME) at PMA
      • Supports DME bypass
      • Supports PLCA RS sub-layer (IEEE802.3cg-2019 CL-148)
  • 100 Base-T1 Interface
    • Based on IEEE 802.3bw-2015
      • MII
      • 4b/3b Encoding/Decoding
      • Data Scrambler
      • Side-Stream Scrambler
      • PHY Control
      • Link Monitor
    • 1000 Base-T1 Interface
      • Based on IEEE 802.3bp-2016
        • GMII
        • 80b/81b Encoding/Decoding
        • Side-Stream Scrambler
        • RS-FEC (450, 406)
        • EEE
        • OAM
        • CL-98 AN
        • PHY Control
        • Link Sync
        • Link Monitor
      • Dynamic Switching
        • Run-time speed switching on-the-fly
      • PMA Bus-Width
        • Configurable PMA bus width: 2 bits for 100/1000BaseT1, serial for 10BaseT1s.
      • Clock, Jitter, Drift
        • Internal and external clock mode
      • Flow Control
        • Pause FC and PFC pause FC
      • Frame Types
        • Ethernet IEEE 802.3 (Type and Length defined)
        • Jumbo frame
        • MAGIC frame
        • Version II frame
        • Pause frame
        • PFC Pause frame
        • Management frame
        • Tagged Frames: Single Tagged (Q-VLAN tag) and Double tagged (S-VLAN tag and Q-VLAN tag)
        • Upper Layer Frames: TCP, UDP, IPV4, IPV6, SNAP, MPLS, FC, MACSEC
      • Custom Frame
        • Proprietary header support
      • MDIO Interface
        • MDIO interface as per Clause-22 and Clause-45

        Block Diagram

        Simulation VIP for Ethernet Base-T1 Block Diagram

        Technical Specifications

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Semiconductor IP