The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol which is part of the Arm® Debug Interface Specification. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms incorporating the latest protocol updates with integrated automatic protocol checks and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SWD runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: SWD v1 and v2 as per Arm Debug Interface specification v6.0 (ADIv6.0).
