SHA3 IP Core

Overview

SHA3 IP Cores perform cryptographic hashing in compliance with the SHA-3 (Secure Hash Algorithm 3) specifications defined in 'FIPS 202'. This standard specifies methods for generating secure hash values using the SHA-3 algorithm. 

SHA3 IP Cores support the SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128, and SHAKE256 functions, and are byte-oriented in their implementation. VHDL is used as the Hardware Description Language of the IP Core. AXI4-Stream interface can be designed and provided upon request.

Key Features

  • supports hashing for functions listed below:
    • SHA3-224
    • SHA3-256
    • SHA3-384
    • SHA3-512
    • SHAKE128
    • SHAKE256
  • is compliant with FIPS 202.
  • has fully stallable input and output interfaces.

Block Diagram

SHA3 IP Core Block Diagram

Deliverables

  • Encrypted Netlist
  • Synthesis Scripts
  • Comprehensive Documentation
  • SHA3 Validation SystemTestbenches in SystemVerilog

Technical Specifications

×
Semiconductor IP