SHA1 64/128 Crypto Core

Overview

SHA-1 IP core implements Secure Hash Algorithms specified in FIPS 180-4 standard. Common cores are available for ASIC and FPGA applications. 

Key Features

  • IP core supports higher frequency and accepts data every 41 or 21 clocks as opposed to every 80 clocks for IPs available in the market.
  • SHA1 supports SHA1 as per FIPS 180-4
  • 64-bit or 128-bit data path interface
  • Padding is added as per the specification to make the message a multiple of 512-bit block
  • SHA1 produces a message digest of 160 bits
  • Accepts a new block every 41 clocks (64-bit data path) or 21 clocks (128-bit data path)
  • Fully synchronous design 

Technical Specifications

Maturity
Available on Request
Availability
Available on Request
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Semiconductor IP