Dolphin s hardened DDRx SDRAM PHY and LPDDRx SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 1600 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin s DDRx and LPDDRx SDRAM Memory Controller IP.
SDRAM DDR3/2 & LPDDR3/2 Hardened PHY - TSMC 55nm ULP
Overview
Key Features
- + Dolphin DDR2/DDR3 PHY IP is fully compliant with the DFI 4.0 Specification
- + Support speeds of up to 1600Mbps with 1.8V and 2.5V Oxide.
- + IP is split into 2 hard macros.
- + One for commands, control and address pins and another for 8-bit data bus.
- + Can support custom number of address bits.
- + Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
- + Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
- + JTAG signals also provided for Mentor/Synopsys and LogicVision
- + Built in Self Test with a Pseudo Random Pattern Generator
- + Built with Scannable flops
- + Can be used in wirebond, flip-chip and cup configurations
Deliverables
- + Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- + Synthesis and STA scripts
- + User guide documents
- + SV/UVM Verification suite with BFM
Technical Specifications
Foundry, Node
TSMC 55nm
Maturity
Pre Silicon
Availability
Yes
TSMC
Pre-Silicon:
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
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