SD4.0 / UHS-II Host Controller & PHY

Overview

Compliant with the following specifications:
- Part 1 Physical Layer Specification Version 5.0
- Part 1 UHS-II Addendum Version 1.02
- Part A2 SD Host Controller Specification Version 4.20

Key Features

+ Support Standard Capacity (SDSC), High Capacity (SDHC) and Extended Capacity (SDXC) cards
+ 1 and 4-bit parallel legacy SD interface, and serial UHS-II interface
+ All bus interface modes: legacy SD (DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50) and UHS-II (FD156, HD312)
+ Data transfer rate up to 104 Mbps with 4 parallel SD data lines
+ Data transfer rate up to 312 Mbps in Half-duplex; 156 Mbps in Full-duplex mode with UHS-II interface
+ Selectable non DMA, Single DMA (SDMA), Advanced DMA 2 (ADMA2) and Advanced DMA 3 (ADMA3)
+ Dual data buffer to improve the data throughput
+ Interfaces to DTI SD PHY, Card Detection (Insertion / Removal)
+ UHS-II data burst retry, Point to point topology for single device
+ SD6.0 Command Queue

Applications

Communications, Data Processing, Industrial, Automotive

Deliverables

Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
Synthesis and STA scripts
User guide documents
SV/UVM Verification suite with BFM

Technical Specifications

Maturity

Pre Silicon

Availability

Yes

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