SD/SDIO/MMC Host Controller

Overview

Key Features

• Compliant with SD Host Controller Spec ver 2.0 and MultiMediaCard Spec ver 4.2/3.X
• Supports SD 1bit and 4bit modes, as well as SPI mode
• Supports MMCplus and MMCmobile specifications
• Provides memory-mapped and i/o access to SD/MMC cards through a Wishbone slave adapter
• Read cache with variable physical size and configurable page size to boost-up card read access performance.
• Interrupt-on-completion handshake eliminates host resources utilization during read operations
• Write FIFO with variable size and configurable thresholds to enable non-blocking operations and prevent back-pressure propagation from card to host
• Supports posted write operations
• Supports SDIO IRQ signaling
• Implements multi-block read and write commands with internal STOP command generation (CMD12) for enhanced throughput
• Supports any data block length
• Supports fast and slow SD cards. SD clock frequency: 0-50+MHz
• Supports hot card insertion and removal
• SD/SDIO/MMC/SPI identification flow implemented by hardware
• Provides command port interface for direct access to the SD/MMC devices and for I/O access to SDIO devices
• Features zero-wait-states on SD bus
• Wide range of configuration options to fine-tune the core according to the system specifications and demands
• Wide range of mask able interrupt events, such as card detection, block transfer termination, command completion, error detection end many more
• Internal implementation of CRC16 for data lines and CRC7 for command line
• Slave System Interface: AHB, OCP, OPB, PLB, WISHBONE, Custom
• No dedicated local memory required
• Compact and cost-effective solution for SoC and PDA

Benefits

• Flexible
• Compact
• Cost-effective

Deliverables

• Verilog Source Code
• Test Bench
• Sample Syntheis scripts
• Dcumentation

Technical Specifications