SD/SDIO Combo Device IP core is an SD memory controller and an SDIO controller with an AHB interface. Combining with the optional our SD/SDIO Combo Device IP provides an integrated SD memory solution which can compact with low power and scalable IP core with a simple, firmware-friendly cost-effective Physical Link interface for memory, i/o and combo devices, such as SD-based memory cards, Mini SD, Micro SD, SDIO Bluetooth devices, SDIO GPS, etc.
SD/SDIO Device IP Core
Overview
Key Features
- SD/SDIO V2.0 Host Physical Layer Compatible
- MMC v 4.X/3.X Compatible
- SD/MMC bus modes of 1bit, 4bit, 8bit, and SPI supported
- Compliant with SD spec 2.00 and SDIO spec 2.00
- Supports SD 1bit and 4bit modes, as well as SPI mode
- 8bit support for future SD spec enhancements
- Supports SDIO features: Suspend/Resume, Interrupt, Read Wait
- Supports Combo cards
- Generic 8/16/32 bit system bus interface
- Set of “Read-Clear” status bits with interrupt mask
- Optional extended data buffering 0-4K bytes.
- Optional read/write data DMA
- Busy signal asserted by hardware, negated by firmware
- CRC7 for commands and optional CRC16 for data integrity in SPI mode
- Supports data block size of 1 byte to 4K bytes
Benefits
- Multi-block read and write
- Supports fast and slow cards. SD clock frequency: 0-50+MHz
- Supports SD clock suspension
- Supports hot card insertion and removal
- Trivial firmware interface
- Compact and cost-effective solution for SoC
Deliverables
- RMM complaint Verilog RTL
- Synthesis scripts
- Test environment
- Technical documentation