SD Express Verification IP is an advanced solution in the market for the verification of SD Express implementations. It can generate all command types. The SD Express monitor acts as powerful protocol-checker, fully compliant with SD specification version 7.0, 7.10 and 8.0(Draft). The SmartDV Verification IP (VIP) for SD Express provides an efficient and simple way to verify the SD Express protocol bus.
SD Express VIP includes an extensive test suite covering most of the possible scenarios and SD Express conformance norms. SD Express VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.
SD Express Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SD Express Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.