IP Catalog > Peripheral IP > Memory Controller & PHY IP > SD IP > SD Controller IP > SD Express Card Verification IP

SD Express Card Verification IP

Overview

The SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

The SD Express Card VIP is fully compliant with Standard SD card v7.00 specifications from SD Organization. The VIP is a light weight VIP with easy plug-and-play interface so that there is not hit on the design time and simulation time.

Key Features

  • Compliant to SD Specification v7.00
  • SD Express card supports NVMe protocol over PCIe Interface
  • Supports SD and PCIe Mode
  • Supports PCIe Gen3 Single lane with Dual simplex point to point serial connection
  • Supports 128/130 encoding with two differential I/O of 8Gpbs transfer, producing upto 985MB/s for each direction
  • Support for Hot plug-in/out
  • Support NVM-Express over PCIe interface
  • Supports Host Memory Buffer by MVMe
  • Supports NVMe with multi queues and no locking mechanism
  • Supports all Capacity of Memory i.e.
  • Standard Capacity SD Memory Card (SDSC)
  • High Capacity SD Memory Card (SDHC)
  • Extended Capacity SD Memory Card (SDXC)
  • Ultra Capacity SD Memory Card (SDUC)
  • All UHS1 modes – SDR50/SDR104/DDR50 supported for backward compatibility
  • Support for all types of speed classes (SC,UHS SC and VSC)
  • Support for Application Performance Classes
  • Supports command queuing
  • Support for Self Maintenance and Cache
  • Support for FULE and Discard
  • Support for LVS and Power Management
  • Support for Extension register
  • Supports Pseudo Initialization mode
  • Supports Password protection (card lock /unlock) through SD mode
  • Supports Card internal Write protect using SD mode
  • Supports CPRM Security through SD mode
  • Supports PCIe Linkup Mode
  • Supports card ownership protection
  • Supports address extension command
  • Support for video class specification
  • Protocol checker that shoots errors in case of violations. Some of the errors are Out of range error, CRC error, Misalignment error , Invalid queue error etc
  • Provides full control to user to enable/disable various types of messages
  • Supports full timing models or bus functional models
  • Supports Dynamic as well as static Error injection scenarios
  • On the fly protocol checking using protocol check function, static and dynamic assertions
  • Provides a comprehensive user API (callbacks) in BFMs
  • Supports advanced System Verilog features like constrained random testing
  • Built in Coverage analysis.
  • Graphical Analyzer to show transactions for easy debugging.

Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of various Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across the VIP
  • Provide complete solution and easy integration in IP and SoC environment

Block Diagram

SD Express Card Verification IP Block Diagram

Deliverables

  • SD Express Memory Card Model
  • SD Express Monitor & Scoreboard
  • SD Express Host Model
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertions & Cover Point Tests
    • Error injection Scenarios Tests
  • Integration Guide, User Manual and Release Notes
  • GUI analyzer to view simulation packet flow.

Technical Specifications

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