IP Catalog > Peripheral IP > Memory Controller & PHY IP > eMMC IP > eMMC PHY IP > SD/EMMC PHY

SD/EMMC PHY

Overview

The SD/EMMC PHY IP supports up to 208MHz which compliant with SDIO and EMMC specification. The SDIO/EMMC PHY includes DLL/Delay lines and IO. I/O input voltage is 3.3V, and signal voltage is within 3.3V/1.8V. Delay line supports dual data rate for DDR50, and single data rate for SDR104.

The DLL/Delay lines in SD/EMMC PHY IP support fine resolution, and the IP support bypass mode to control the delay lines.

Key Features

  • Include 1 clock, 1 bi-directional CMD, and 4 bi-directional DATA channel
  • Design in GLOBALFOUNDRIES 22nm FDX process
  • Data rate range: 50M~104MB/s
  • Supports up to 208MHz clock
  • Signal voltage supports 3.3/1.8V
  • IO driver supports 33/50/66/100Ω terminations, and default is 50Ω
  • Include high speed IOs and DLL/Delay lines
  • DLL/Delay lines support fine resolution
  • Core area: 62628.5um^2 (not include IO)
  • Power consumption:
    •   9mW@200MHz/signal voltage 1.8V

Block Diagram

SD/EMMC PHY Block Diagram

Technical Specifications

GLOBALFOUNDRIES
Pre-Silicon: 22nm FDX
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