SATA Synthesizable Transactor

Overview

Key Features

• Supports SATA specs 2.5/2.6/3.0/3.1/3.2/3.3/3.4/3.5.
• Supports 1.5, 3 and 6 Gbps speeds.
• Supports Port Multiplier Discovery and Enumeration.
• Supports TBI interface with following bits
  • 10 bit
  • 20 bit
  • 40 bit
• Supports the PIPE interface
• Disparity checking.
• Kcode & Dcode validity and alignment.
• 8b/10b Encode and Decode functions.
• Controls to inject bit errors.
• OOB sequence generation and checking.
• Digital SERDES model included.
• Callbacks for use in directed test writing.
• Selectable as Host or Device BFM.
• Complete Link Layer state machine.
• Selectable Primitive CONT and fill substitution processing.
• Selectable data scrambling option.
• Configurable Receive and Transmit fifo latencies.
• 8b/10b encoding and decoding, Error injection.
• Configurable OOB signals and speed of operation.
• Configurable phy layer timers.
• User defined primitive transmission.
• Single or multi-bit error injection.
• User defined primitives & frame transmission.
• Supports link layer power modes.
• SYNC injection during FIS transfer.
• Randomized/directed CRC error injection and checking.
• Ability to enable/disable scrambling on the fly.
• Programmable enable/disable & duration of DMAT, CONT and HOLD primitives.
• Callback functions for state transitions, primitive and FIS reception/transmission
• OOB transmission/reception and speed change.
• Supports LBA with HDD size configuration.
• APIs providing backdoor access to HDD.
• Programmable auto-activate support using configuration.
• Supports all standard ATA command sets including NCQ.
• Configurable FIS latencies, FIFO depths and FIS size.
• Supports PIPE interface.
• Supports 8,16,32,64 bit SERDES interface.
• Supports Asynchronous notification.
• Supports Asynchronous Signal Recovery.
• Supports Speed Switching/Negotiation.
• Set Features support.
• Device Configuration Overlay.
• Software Settings Preservation and Hardware Feature Control support.
• Supports Staggered Spin up.
• Supports the Non 512 Byte Sector Size.
• Support for Enclosure Management/Services is available.
• Supports HDD activity activation.
• Ability to Automatic Partial to Slumber Transitions.
• Supports DHU Specific Operation.
• Rebuild Assist is supported.
• Supports Intermixing of Non-native queued commands with Native Queued commands.
• Enabled Hybrid Information Feature.
• Device Signature return Feature.
• Supports SATA Logs.
• Optional DC-IDLE pin
• Supports FPDMA Zone management commands.
• Supports Queued version of ACS-4 Zero EXT command.
• Supports Receive FPDMA Queued to support ZAC.
• Supports Data Set Management aligned with ACS-4 and Data Set Management XL command.
• Supports ZAC Management Logs for NCQ Non data and Send/Receive FPDMA commands.
• Supports Out of band management control structures
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• SATA Verification IP comes with complete testsuite to test every feature of SATA specification.

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the Sata testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications