Gigacom's VSL340 PHY is suitable for both Host and Device applications within a Serial ATA system. The VSL340 PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to a Serial ATA Link Layer where the 8b10b encoding and decoding of the data is done. Recovered data is provided using SATA compliant D-word alignment. The VSL340 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products.
The VSL340 PHY is comprised of a hardened GDSII Physical Medium Attachment (PMA) sublayer containing the SerDes, plus a soft Physical Coding Sublayer (PCS) Verilog module that is connected to the hard macro at the PMA interface. The PCS, when coupled with the hardened PMA SerDes macro, provides a Serial ATA PHY with compliant signals for the end customer. Since the VSL PHY family includes many test features and capabilities that are not part of the Serial ATA specification, additional pins from the PMA layer are also available.
SATA PHY
Overview
Key Features
- Serial ATA II Revision 2.6 compliant
- Gen1i, Gen1m, Gen2i, Gen2m compliant
- Gen1x, Gen2x compatible
- Initialization and power saving modes
- Full ±5700 ppm data tracking capability in all modes (with elastic buffer build option)
- Transmission jitter generation and receiver jitter tolerance which exceed Serial ATA jitter specifications
- 10 or 20 bit interface (build option)
- Serial ATA compliant command and status signals
- K28.5 comma detection
- ALIGN detection and alignment
- Selectable lane polarity inversion
- Host or Device applications
- Programmable serial transmit amplitude
- Programmable serial receiver equalization
- Status pins for checking PHY functionality
- Integrated bandgap
- Automatic driver/receiver impedance calibration
- Very small size
- Extensive built in testability
- At-speed BIST circuitry with various PRBS and 8B10B patterns
- Multiplexed scan for testability of all digital logic
- Eye width mapping and on-chip jitter generation capability
- Loop back modes
- Serial Control Register
- Support for DC and AC JTAG (AC EXTEST)
Benefits
- Low Risk - Silicon proven today in multiple foundries and processes with Extensive Si characterization data
- Excellent Interoperability - LC tank oscillator that gives low noise and jitter
- Superior Noise Immunity - Fully differential circuitry and Voltage Regulator for enhanced noise immunity
- Low Power - As low as 60mW per lane at 3.125Gb/s
- Minimal Area - for Wire bond as well as flip-chip package
- Improve Test Coverage - Multiple loopback modes with 12 built-in patterns
- Scan built in to all digital,Serial Control Register (SCR) for simplified testing, JTAG support (DC and AC )
- Lowest Total Cost of Ownership
- Customization/ Integration support
Block Diagram
Applications
- PCs, Laptops, Servers, Storage Devices
Deliverables
- Abstract - LEF
- Behavioral Model -Verilog
- Timing Model -.lib
- High-speed IO Model - hSpice
- LVS Netlist - cdl
- Physical database - GDSII
- Documentation - pdf
Technical Specifications
Foundry, Node
TSMC 65nm GP, TSMC 65LP, Globalfoundries 65nm LP. Globalfoundries 40nm LP. Globalfoundries 55nm LP. Silicon proven in TSMC 28nm HPC/HPC+
Maturity
In Production
Availability
Immediately
GLOBALFOUNDRIES
Pre-Silicon:
40nm
LP