SATA II PHY IP, UMC 55nm SP process
Overview
Serial ATA I, II PHY, UMC 55nm SP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- Serial ATA (SATA) I/II PHY IP CORE
- SATA III PHY IP, Gen-3, UMC 55nm SP process
- SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
- SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
- SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process