IP Catalog > Interface IP > Memory Interface IP > SAS IP > SAS Controller IP > SAS Verification IP

SAS Verification IP

Overview

SAS Verification IP provides an smart way to verify the SAS bi-directional bus. The SmartDV's SAS Verification IP is fully compliant with SAS 2.1, SAS 3.0, SAS 4.0,SAS 5.0, SAS Protocol Layer SPL 1.0, SPL 2.0, SPL 3.0, SPL 4.0 and SPL 5.0, SPL 5.3, SPL 5.4 and SPL 5.5 and SPL 5.8 and 5.10 of the SAS Specification and provides the following features.

SAS Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SAS Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports trained 1.5,3,6,12 and 22.5 Gbps speeds.
  • Supports untrained 1.5,3 and 6 Gbps speeds.
  • Supports Narrow ports and wide ports.
  • Supports Reset sequences
  • Supports Expander device model function.
  • Supports Retimer device model
  • Supports Discover process
  • Supports Phy power conditions
  • Supports Successful low phy power conditions handshake sequence.
  • Supports SATA Spin-up and Port Selectors.
  • Supports SAS Dword mode and Packet mode.
  • Complete Disparity checking.
  • Complete Kcode & Dcode validity and alignment.
  • Complete 8b/10b Encode and Decode functions.
  • Complete 8b/10b encoding and decoding error injection.
  • Supports OOB sequence generation and checking.
  • Configurable OOB signals and speed of operation.
  • Configurable phy layer timers.
  • Supports BMC Encoding.
  • Supports Forward error correction encoding & decoding.
  • Supports Interleaved SPL Packet mode encoding & decoding.
  • Supports SNW-3 Phy capabilities bits.
  • Supports Spread Spectrum Clocking Modulation techniques.
  • Supports Expander device handling of connection.
  • Supports Phy reset sequences.
  • Supports SAS speed negotiation sequence
  • Supports Train_Tx-SNW & Train_Rx-SNW for SAS Dword mode and Packet mode.
  • Complete dword synchronization,SPL packet synchronization and resynchronization phy layer state machines
  • Complete transmitter training and active phy transmitter adjustment phy layer state machines
  • Supports Management application client model for APTA.
  • Supports primitive encoding, binary primitive coding, and extended binary primitive coding.
  • Supports Physical link rate tolerance management
  • Supports Bit order of CRC and scrambler for SAS Dword mode and Packet mode.
  • Supports Address frames
  • Supports Link reset sequence
  • Supports STP, SSP& SMP Link layer Connections.
  • Supports link layer Rate matching for SAS Dword mode and Packet mode.
  • Supports SAS domain changes Complete power control, identification and hard reset link layer state machines
  • Complete SAS logical phys, expander logical phys, SSP, STP and SMP link layer state machines
  • Supports configurable for port control mode page
  • Supports SSP frame fields
  • Supports STP frame fields
  • Supports SMP frame fields
  • Complete overall control and phy control state machine.
  • Supports SSP,STP and SMP frame fields errors.
  • Supports SCSI,ATA and management frame transaction.
  • Supports Parameter Storage, Mode Pages and Log Pages.
  • Callbacks for use in directed test writing.
  • Selectable Primitive CONT and fill substitution processing.
  • Configurable Receive and Transmit fifo latencies.
  • User defined primitive transmission.
  • Single or multi-bit error injection.
  • User defined primitives & frame transmission.
  • Randomized/directed CRC error injection and checking.
  • Ability to enable/disable scrambling on the fly.
  • Supports LBA with HDD size configuration.
  • APIs providing backdoor access to HDD.
  • Programmable auto-activate support using configuration.
  • Supports standard SCSI, SMP and STP commands.
  • Supports Expander device model features & Expander device handling of connections.
  • Supports Zone permission configuration.
  • Supports STP flow control.
  • Configurable FIS latencies, FIFO depths and FIS size.
  • Software Settings Preservation and Hardware Feature Control support.
  • Supports the Non 512 Byte Sector Size.
  • Supports HDD activity activation.
  • Ability to Automatic Partial to Slumber Transitions.
  • Supports DHU Specific Operation.
  • Rebuild Assist is supported.
  • Enabled Hybrid Information Feature.
  • Device Signature returns Feature.
  • Supports SATA features.
  • Callbacks in Host, Device and monitor for user processing of data.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • SAS Verification IP comes with complete testsuite to test every feature of SAS specification.
  • Functional coverage for complete SAS features.

Benefits

  • Faster testbench development and more complete verification of SAS designs.
  • Easy to use command interface simplifies testbench control and configuration of Root complex and End point.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

SAS Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the SAS testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

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