SAS INITIATOR IIP

Overview

The SAS Initiator IP core is fully compliant with Serial ATA SCSI 5.0 Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. SAS Initiator IIP is proven in FPGA environment.The initiator interface of SAS can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SAS INITIATOR IIP is supported natively in Verilog and VHDL

Key Features

Supports SPL 1.0/2.0/3.0/4.0/5.0 Specs
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices
Supports SAS 1.5,3,6,12 and 22.5 Gbps data transfer rates
Supports SATA 1.5,3 and 6 Gbps data transfer rates
Supports native 32bit PHY Interface
Supports 8b/10b Encoding
Supports 10 bit, 20 bit ,40 bit parallel interface
Supports Narrow ports and wide ports
Supports Identify and Reset sequences
Supports SSP , SMP and STP protocols
Supports Physical link rate tolerance management
Supports STP, SSP& SMP Link layer Connections
Selectable Primitive CONT and fill substitution processing
Supports STP flow control.
Supports SAS Dword mode and Packet mode
Supports Forward error correction encoding & decoding.
Supports Interleaved SPL Packet mode encoding & decoding.
Complete dword synchronization,SPL packet synchronization and
resynchronization phy layer state machines
Supports link layer Rate matching for SAS Dword mode and Packet mode
Supports Address frames
Supports all PHY power conditions and management
Supports DMA and PIO commands
Device Signature returns Feature
Supports SATA features
Hardware support for
- 48-bit address set
- 8b/10b coding and decoding
- CRC generation and checking
- Auto insertion of HOLD primitives
- Native Command Queuing (NCQ)
- Port Multiplier, Port Selector
- First Party DMA (FPDMA)
Implements the shadow register block and the serial ATA status and control registers

Benefits

Single site license option is provided to companies designing in a single site.
Multi sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The SAS Initiator interface is available in Source and netlist products.
The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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