The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devices for test, initialization and other low bandwidth purposes. The Veriest Register Indirect RAM Access is ideal for IP developers to provide access to shared RAMs in which the CPU needs to have limited access whereas another RAM client has priority access. After a simple register configuration setup by the CPU, the RAMs can be accessed for read and write through the AHB slave interface.
Register Indirect RAM Access
Overview
Key Features
- Easy integraton
- AMBA AHB 3.0 Compatible
- AHB Reads, Writes
- Burst Types: Single, INCR, INCR4, INCR18, INCR16
- Transfer size 32-bit aligned only
- Configurable address bus width (32-bit / 64-bit)
- Configurable data bus width (32-bit / 64-bit / 128-bit)
- Configurable number of RAMs to access
- Configurable RAM width
- Low latency
Benefits
- Low Gate Count
- Low Power Consumption
- Fully Verified
- Spyglass Lint Validated
- Standards Compliant
Block Diagram
Applications
- General System on Chip Use
Deliverables
- Synthesizable Verilog RTL
- Verilog test bench and test cases
- Detailed block diagram and technical documents
Technical Specifications
Maturity
Fully Verified
Availability
Now