A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error correction.
Reed Solomon Decoder IP Core
Overview
Key Features
- Continuous, very high-speed, time-domain Reed-Solomon decoding algorithm.
- Supports different Reed-Solomon coding standards.
- Code rate can be dynamically varied
- Parameterizable bits per symbol (M).
- Programmable codeword length (NVAL) with parameterizable maximum value (N).
- Programmable number of errors (TVAL) with parameterizable maximum value (T).
- Shortened codes supported (NVAL,TVAL).
- User configured primitive field polynomial.
- User configured generator polynomial.
- Synchronous design.
- Predictable decoder latency.
- Status and performance monitoring signals
Benefits
- Flexible
- Compact
- Cost-effective
Deliverables
- Verilog Source Code
- Test Bench
- Sample Syntheis scripts
- Dcumentation
Technical Specifications
Foundry, Node
any
Maturity
production
Availability
now
Related IPs
- Reed Solomon Decoder
- Reed Solomon Forward Error Correction Encoder Decoder
- BCH Encoder and Decoder IP Core
- Reed Solomon Codec (Errors-only)
- Reed Solomon Encoder IP Core
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core