PUF IP

Overview

The patented PUF design generates a unique identity based on quantum tunnelling current variations through the gate terminal in any standard CMOS process. The source of the randomness stems from the device’s oxide thickness variations and random distribution of defects (traps) in the gate oxide. A PUF realised based on these unpredictable and unclonable variations is the basis for a hardware root-of-trust on which a security architecture can be built.

Key Features

  • Certification & compliance
    • PSA Level 2 Ready
    • CC EAL4+ compliant
  • Environmental operating data
    • QDID™ PUF has been tested extensively under varying environmental conditions and achieved a lifetime operating time of greater than 25 years between −40°C to 125°C
  • Randomness health test
    • NIST SP 800-22 randomness
    • NIST SP 800-90B entropy
  • Process nodes
    • QDID™ PUF IP has been verified on major fabs (TSMC, GF, UMC) across Bulk CMOS, FDSOI, FinFET process technologies (55nm down to 12nm)

Benefits

  • Secure provisioning
    • QDID™ PUF removes the challenges associated with secure provisioning through key injection on a factory floor, reducing the cost and complication of HSMs as well as the risks associated with trusting third parties
  • Secured identities
    • Identities are not stored in the memory, but just created on-the-fly, making them resistant against side-channel attacks on memory
  • High entropy seeds
    • QDID™ PUF’s source of entropy is based on a quantum phenomenon and resistant to machine learning-based attacks of the entropy source.
    • Customisable number of seeds of security strength up to 256 bits can be generated on demand.
  • Built-in resistance to side channel attacks
    • The PUF IP has been developed with a “secure by design” approach which has built in resistance to secret leakage through countermeasures and attack detection schemes

Video

Overcoming challenges in PUF development

Applications

  • Key generation
  • Device identification
  • Device authentication
  • Device provisioning
  • Post-quantum cryptography
  • Supply chain security

Technical Specifications

Foundry, Node
Global Foundries, UMC, TSMC 55nm-22nm
Maturity
Silicon proven, multiple generations.
Availability
Now
GLOBALFOUNDRIES
Pre-Silicon: 12nm , 14nm , 28nm
Silicon Proven: 22nm , 55nm
TSMC
Silicon Proven: 22nm , 40nm G , 40nm LP , 55nm FL , 55nm G , 55nm GP , 55nm LP , 55nm NF , 55nm ULP , 55nm ULPEF , 55nm UP , 65nm G , 65nm GP , 65nm LP
UMC
Silicon Proven: 28nm , 40nm
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Semiconductor IP