QOI Lossless Image Compression Decoder

The QOID Core is a decoder that implements a highly efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format (QOI) specification, version 1.0.

The QOI algorithm compresses RGB or RGBA images with 8 bits per color without any loss. It has a compression efficiency close to that of the PNG compression, at a fraction of the computational complexity. Capitalizing on the simplicity of the QOI algorithm, the QOID decoder core can decompress images at a very high speed and with minimal silicon resources.

The core occupies approximately 15,000 equivalent NAND2 gates and can decode one pixel per clock cycle. A single core instance can decompress images at rates sufficient for UHD 4k30 video even in low-end FPGAs, 4k60 in mid-range FPGAs, and 8k30 or 60 in modern ASIC technologies.

The QOID core is designed for ease of use and integration and adheres to coding and verification best practices. It requires no assistance from a host processor and uses simple handshake interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.

• QOI Image Format
  • Lossless compression
  • Supports RGB and RGBA, 8-bit per color images
  • Compression performance similar to that of PNG with a fraction of the computational complexity
• QOID IP Core 
  • QOI decompression with a compact and high-throughput hardware decoder
  • Receives raw header-less QΟΙ files
    • Optional QOI header processing 
  • Supports RGB images
    • RGBA support can be added on request
• High-Throughput
  • 1 pixel per clock-cycle throughput 
  • A single core can process UHD 4k60 in mid-range FPGAs, and 8k60 on modern ASIC technologies
• Compact and Low-Power
  • Approximately 15,000 gates 
• Deliverables
  • VHDL or Verilog RTL source code or targeted FPGA netlist
  • Verilog can be made available on request 
  • C-model for test vectors generation 
  • Integration Test-Bench 
  • Simulation & synthesis scripts