QDR4 Memory Model

Overview

QDR4 Memory Model provides an smart way to verify the QDR4 component of a SOC or a ASIC. The SmartDV's QDR4 memory model is fully compliant with standard QDR4 Specification and provides the following features. Better than Denali Memory Models.

QDR4 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

QDR4 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports QDR4 memory devices from all leading vendors.
Supports 100% of QDR4 protocol standard CY7C4142KV13.
Supports for 144-Mbit density (8M × 18, 4M × 36)
Supports for Eight-bank architecture enables one access per bank per cycle
Supports for Two-word burst on all accesses
Supports for Dual independent bidirectional data ports
Supports for Double data rate (QDR4) data ports
Supports concurrent read/write transactions on both ports
Supports for Single address port used to control both data ports
Supports for QDR4 address signaling
Supports for Single data rate (SDR) control signaling
Supports for High-speed transceiver logic (HSTL) and stub series terminated logic (SSTL) compatible signaling (JESD8-16Acompliant)
Supports for Pseudo open drain (POD) signaling (JESD8-24 compliant)
Supports for Programmable for clock, address/command, and data inputs
Supports for Internal self-calibration of output impedance through ZQ pin
Supports for Bus inversion to reduce switching noise and power
Supports for Programmable on/off for address and data
Supports for Address bus parity error protection
Supports for Training sequence for per-bit de skew
Supports for On-chip error correction code (ECC) to reduce soft error rate (SER)
Supports all the QDR4 commands as per the specs.
Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Protocol checker fully compliant with QDR4 Specification CY7C4142KV13.
Models, detects and notifies the test bench of significant events such as transactions, warnings, and timing protocol violations.
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Constantly monitors QDR4 behavior during simulation.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of QDR4 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the QDR4 testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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