QDR2 Memory Model

Overview

QDR2 Memory Model provides an smart way to verify the QDR2 component of a SOC or a ASIC. The SmartDV's QDR2 memory model is fully compliant with standard QDR2 Specification and provides the following features. Better than Denali Memory Models.

QDR2 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

QDR2 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports QDR2 memory devices from all leading vendors.
Supports 100% of QDR2 protocol standard CY7C1314CV18.
Supports for Separate independent read and write data ports with concurrent read and write operation
Supports for Full data coherency, providing most current data.
Supports for Synchronous pipeline read with self-timed late write.
Supports for Registered address, control and data input/output.
Supports for QDR (Double Data Rate) Interface on read and write ports.
Supports for Fixed 4-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Supports for Two input clocks (K and K) for accurate QDR timing at clock rising edges only.
Supports for Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
Supports for Two echo clocks (CQ and CQ) to enhance output data traceability.
Supports for Single address bus.
Supports for Byte write function.
Supports for Simple depth expansion with no data contention.
Supports for Programmable output impedance.
Supports for Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports
Supports for Separate Port Selects for Depth Expansion
Supports for Synchronous internally Self-timed Writes
QDR II operates with 1.5 Cycle Read Latency when Delay Lock Loop (DLL) is enabled
Operates similar to a QDR I Device with one Cycle Read Latency in DLL Off Mode
Supports for Available in x18, and x36 Configurations
Supports for Variable Drive HSTL Output Buffers
Supports all the QDR2 commands as per the specs.
Supports for Delay Lock Loop (DLL) for accurate Data Placement
Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Protocol checker fully compliant with QDR2 Specification CY7C1314CV18.
Models, detects and notifies the test bench of significant events such as transactions, warnings, and timing protocol violations.
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Constantly monitors QDR2 behavior during simulation.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of QDR2 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the QDR2 testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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