NetTimeLogic’s PPS Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a Pulse per Second input. The whole algorithms and calculations are implemented in the core, no CPU is required. This allows running PPS synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.
Pulse Per Second Slave (PPS) core
Overview
Key Features
- PPS Slave Clock
- Input signal filter
- PPS supervision
- PPS duty cycle analysis, width can be read via register
- Synchronization accuracy: +/- 25ns
- AXI4 Light register set or static configuration
- Timestamp resolution with 50 MHz system clock: 10ns
- Hardware PI Servo
Benefits
- Coprocessor handling PPS synchronization standalone in the core.
- Simple interface
Block Diagram
Applications
- Distributed data acquisition
- Ethernet based automation networks
- Automation
- Robotic
- Automotive
- Test and measurement
Deliverables
- Source Code (not encrypted, not obfuscated)
- Reference Designs
- Testbench with Stimulifiles
- Configuration Tool
- Documentation
Technical Specifications
Availability
Now