Protocol controller IP for CAN / CAN FD

Overview

The M_CAN is a CAN IP module that can be realized as a standalone device, as part of an ASIC or on an FPGA. It performs communication according to ISO11898-1:2015. It supports Classical CAN and CAN FD (CAN with Flexible Data-rate). Additional transceiver hardware is required for connection to the CAN physical layer. The message storage is intended to be a single or dual-ported Message RAM outside of the module. It is connected to the M_CAN via the Generic Master Interface. Depending on the chosen integration, multiple M_CAN controllers may share the same Message RAM. The Host CPU is connected via the 32-bit Generic Interface.

Key Features

  • Support of Classical CAN and CAN FD according to ISO 11898-1:2015
  • Up to 64-byte payload for faster transmission of large data fields
  • Support of CAN FD Light:
  • standardization is ongoing by the by CiA (CAN in Automation).
  • Multiple M_CAN modules can access one shared memory
  • Smart message handling reduces CPU load
  • Connectable to customer-specific Host CPUs with 8/16/32-bit generic CPU interface
  • Bit rates up to 8 Mbit/s, depending on application and used transceiver
  • Safe communication with 17/21bit CRC (CAN FD) or 15bit CRC (CAN)
  • Functional Safety Ready
  • M_CAN has been developed as Safety Element out of Context (SEooC) according to ISO 26262-11:2018, Clause 4
  • Safety Manual and FMEDA available on request.
  • M_TTCAN additionally supports Time-Triggered CAN for real-time applications according to ISO 11898-4

Block Diagram

Protocol controller IP for CAN / CAN FD Block Diagram

Deliverables

  • Deliverables for ASIC design
    • Well documented VHDL source code
    • VHDL test bench environment
    • M_CAN User’s Manual (programmer's view)
    • M_CAN System Integration Guide (designer's view)
    • M_CAN Module Integration Guide (designer's view)
    • M_CAN Conformance Test Report
  • Deliverables for FPGA design
    • Encrypted VHDL source code
    • VHDL source code of an example system design with RAM and an example arbiter instance
    • Source code FPGA internal bus interface
    • M_CAN User’s Manual (programmer's view)
    • M_CAN System Integration Guide (designer's view)
    • M_CAN FPGA Integration Guide (designer's view)
    • M_CAN Conformance Test Report
    • Programming examples for fast start up

Technical Specifications

Availability
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Semiconductor IP