Power on Reset IP, Input: 3.3V, Vrr=2.81V, Vfr=2.81V, UMC 55nm SP process
Overview
Vrr=2.81V Vfr=2.81V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset,special request, UMC 55nm SP/RVT LowK Logic Process
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm