Power on Reset IP, Input: 1.2V, Vrr=0.8V, Vfr=0.65V, UMC 55nm LP process
Overview
Vrr=0.8V, Vfr=0.65V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
Technical Specifications
Foundry, Node
UMC 55nm LP
UMC
Pre-Silicon:
55nm
Related IPs
- GLOBALFOUNDRIES 40nm LP 2.5V/1.1V Power on Reset
- 128x8 Bits OTP (One-Time Programmable) IP, TSMC 55nm LP 1.2V/2.5V & ULP 0.9V/2.5V Mixed-Signal, General Purpose Process
- Power on Reset 1.2V
- Vrr=0.8V,Vfr=0.65V,input VCC=1.2V, 1.2V Power On Reset; UMC 55nm e-flash Logic Process
- Power On Reset (Vcc=1.8v,Reset Time=1,2,3 Sec)
- SMIC 0.13um 1.2V Power On Reset