The agilePOR GP is a Power-On-Reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Power-On-Reset Circuit
Overview
Key Features
- Start-up Time: max 10us
- Configurable Threshold
- Programmable Delay
- Uses Hysteresis to avoid false resets in noisy environments
- Current Consumption1: typ 100nA
- Customizable design for simple SoC integration
Benefits
- Hysteresis
- - Avoids false resets due to noisy environments
- Configurable thresholds
- - Both upper and lower thresholds are programmable
- - Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions
Block Diagram
Applications
- Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system.
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Foundry, Node
Intel
Maturity
Available on request
Availability
Now
Intel Foundry
Pre-Silicon:
16nm