Power On Reset Circuit
Overview
The designated IP is a power on reset circuit intended for integration into 130nm CMOS technology System on Chips. RESET threshold value is determined by 2VTN+VTP over a temperature range of -40 to 120°C. When VDD falls below the reset threshold, RESET goes low and holds the reset signal in high state for 10us after VDD rises above the threshold.
Key Features
- Fully integrated, compact design
- 3.3V output voltage
- 3.3V± 10% power supply
- Area 0.003373mm2
- CMOS 130nm 1P8M,3.3V IO MOS
- No external component
Benefits
- Threshold voltage determined by 2VTN+VTP
- Fast time to market
Deliverables
- GDSII & CDL Netlist
- .lef for PnR
- Datasheet
- Technical Reference Manual, Design Document
Technical Specifications
Foundry, Node
0.13u Tower
Maturity
Silicon Implemented
Availability
Immediate
TSMC
Pre-Silicon:
130nm
LP
Tower
Pre-Silicon:
130nm