Phase-frequency detector (PFD) forms control signal for VCO tuning. PFD compares phases of divided VCO signal and divided reference oscillator signal and detects phase difference. Charge pump generates pulses for loop filter. The CP output stage is an amplifier equalizing a buffer reference voltage of CP output current adjustment with a loop filter voltage; and an amplifier minimizing the disbalance of the charging/discharge current in loop filter capacitors.
Reference frequency 24.84 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
PLL CMOS phase-frequency detector with CMOS charge pump
Overview
Key Features
- iHP SGB25V
- Input signals with low amplitude
- Low disbalance of output current
- Minimum disbalance of the charging/discharge current in loop filter capacitors
- Portable to other technologies (upon request)
Applications
- Phase-locked loop synthesizer
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
iHP SiGe BiCMOS 0.25 um
Maturity
Pre-silicon verification
Related IPs
- PLL CMOS phase-frequency detector with ECL charge pump
- PLL ECL phase-frequency detector with ECL charge pump
- 0.1 to 25 MHz Phase-frequency detector with charge pump
- 24.84 MHz Phase-frequency detector with charge pump (input amplitude 150…210 mV)
- PLL ECL phase-frequency detector with ECL charge pump
- 1 to 20 MHz Phase-frequency detector and charge pump