Physical Layer Interface Core

Key Features

• Fully Compliant with Rapid Interconnect Specification Rev 1.1, 3/2001 prescribed by Rapid Trade Association.
• 32-bit standard Host/Link Interface.
• Full Duplex Independent Transmit and Receive Data Path.
• Dual Data Rate (DDR): 62.5-125 MHz.
• Auto scaling 8/16 bit Ports.
• Respects 32-bit boundaries.
• Rx Queuing: 16 X 128 X 32 or 8 Kbytes of internal buffer.
• Tx Queuing: 8 X 128 X 32 or 4 Kbytes of internal buffer.
• Maximum Packet Length: 276 bytes.
• Minimum Packet Length: 8 bytes.
• Supports a Very Highly Reliable Error Handling Scheme.
• CRC-16 Polynomial.
• Incorporates Intermediate CRC for Packet Length of 80 bytes or greater.
• Upto 8 Unacknowledged Packets.
• 32-Bit Internal Data Path.
• Supports: PACKET RERTY, PACKET NOT ACCEPTED, STOMP, TIME-OF-DAY SYNCHRONIZATION, TRAINING and THROTTLE.
• Separate Management Interface (CSRs/CARs).
• Data Rate 250-500 Mbps per LVDS Pin Pair; Upto 8 Gbits per sec throughput.
• Outputs 32-bits of Data to User Interface.
• Full Control of User Interface bus by user.
• Tx and Rx sections designed for minimum latency between the input and output.
• Smart Bandwidth Utilization (Designed for minimum latency between Link and Fabric, Intelligent EOP avoidance between Back-to-Back Packets).
• Fully automated Test Bench for checking for error-free packets.
• 3 Clock Domains 1 for Management, 2 for Fabric and Link Interface.

Benefits

• Targeted FPGA Xilinx Virtex-II Family
• Clock Frequency: 62.5-125 MHz
• LP-LVDS Buffers (for Fabric end interface)

Deliverables

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
• Test Bench Environment: Verilog

Technical Specifications