The RapidIO™ is a packet - switched interconnect intended primarily as an intra - system interfaces for a chip-to-chip and board-to-board communications at Gigabyte per second performance levels. Developed as an open standard, the RapidIO™ architecture addresses the needs of present and future systems. RapidIO™ is focused as a processor, memory and memory mapped I / O interfaces optimized for use inside the chassis.
This high performance low pin - count packet switched system level interconnect provides highly reliable error handling scheme whilst transferring packets between processing elements via the RapidIO™ Fabric.
In the diagram below, the User Application sends data in chunks of 32 bits to the core, which composes and queues the packets in the RapidIO™ format, before transmission to the Fabric. Similarly, the Fabric sends RapidIO™ packets to the chip, which in turn queues and sends data to the User Application via a Microcontroller Interface.
Product Specifications :
- Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
- Test Bench Environment : Verilog
- Targeted FPGA Xilinx Virtex - II Family
- Clock Frequency : 62.5 - 125 MHz
- LP - LVDS Buffers (for Fabric end interface)
Product Options :
- Adaptations :
- 16 / 32 bit PCI or AMBA Host Interface Possible.
- AMBA Possible.
- Add - ons : Nil.
