1394b PHY IP Core

The 1394b PHY core includes all functionality needed to meet the AS5643 protocol, and provides a complete IP solution for the PHY layer of the 1394b. The 1394b core includes all functionality needed to meet the 1394b and AS5643 support specification, including: comma alignment, 8b/10b encode/decode, primitive decode, scrambling, port state machine, connection manager, arbitration controller, elastic FIFO, and phase FIFO.

At the physical layer, the core of 1394b is built for connecting to FPGA/ASIC embedded SERDES, discrete SERDES parts, or general-purpose IO with AS5643 performance protocol. The Link Layer interface of 1394b PHY IP’s core provides the industry standard PHY-Link interface. This PHY-Link interface connects directly to New Wave Design’s Link Layer IP cores, discrete Link Layer integrated circuits, or to custom logic developed by the end user.

This core is targeted towards Mil1394 aerospace and defense applications and has been used on a wide range of FPGA devices at varying operating rates. The core comes with test-benches and example code, making design integration a straightforward task.

• AS5643 compliant interface
• Supports S100/S200/S400 data rates
• Configurable number of ports per PHY instantiation
• Configurable number of PHYs in a single FPGA
• Standard PHY-Link interface Mil1394 targeted PHY layer implementation

• Increase interface port density while lowering size and power
• Additional diagnostics and programmable operation features
• Leverage proven technology for standard interface implementation

• Vehicle System – Remote Node
• Vehicle System – Vehicle Management Computer Avionic Mission Systems

• Core is delivered in netlist format including constraint files