The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Gen5 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.
The PLL macro is implemented in Analog Bits’proprietary architecture that uses core and 1.8V IO devices.
With all components integrated, jitter performance and standby-power are significantly improved.
SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 24 25 MHz Input Frequency in Bypass Mode fBYPASS 100 MHz Output Frequency FOUT 5 100 2400 MHz Output Duty Cycle tDO 48 52 % Lock Time tLOCK 10 µs Reset Time tRESET 1 µs PLLOUT Random Jitter -- PCIe Gen4 RJPCIe4 0.5 ps-RMS PLLOUT Random Jitter -- PCIe Gen5 RJPCIe5 0.15 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -5000 0 ppm Area A 0.12 sq. mm Total Power IDD 12 20 mW Standby Power IBG 0.5 1 mW Output Load CL 100 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C Table 1: SSCG PLL Operational Range