PCIe Gen 6 controller IP

Key Features

Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
Supports SerDes Architecture PIPE 10b/20b/40b/80b width
Supports original PIPE 8b/16b/32b/64b/128b width
Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
Supports PCIe 6.0 to PCIe 1.0 speeds
Supports Forward Error Correction (FEC) – Lightweight algorithm for low latency
Supports L0p Low Power mode
Up to 4-bit parity protection for data path
Supports Clock Gating and Power Gating

Mature: Compliance-proven IP, with customer SoCs in volume production over many generations
Application Optimized: IP features optimized for key verticals like storage, automotive, enterprise, and AI/ML, configured to your specific needs with minimal gate count
Ease of Use: Fully verified pre-integrated IP delivery, with firmware and testbenches for rapid bring-up