PCIe 7.0 Controller
Overview
The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6.0 and 5.0, as well as version 6.2.1 PHY Interface for PCI Express (PIPE) specification.
Key Features
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/
- completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
- Supports multiple virtual channels High Efficiency Rx/Tx Interface
- Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
- Advanced RAS features
- Optional IDE security with AES-GCM encryption, decryption and authentication
Deliverables
- IP Files
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI (Wizard)
- Full Documentation
- Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project and DC constraint files (ASIC)
Technical Specifications
Foundry, Node
Any