PCIe 5.0 Customizable Embedded Multi-port Switch

Overview

Rambus PCIe 5.0 Multi-port Switch is a customizable, Embedded PCIe Switch designed for ASIC and FPGA implementations enabling the connection of one upstream port and multiple downstream ports with a large choice of configurations. Rambus PCIe 5.0 Multi-port Switch is the first embedded switch available on the market and enables designers to use fewer PHYs, saving latency, power consumption and bill-of-material. PCIe switches manage dataflow within a device, delivering the flexibility, scalability and configurability required to connect a large pool of drives or networks.

Key Features

Switching Logic:

1 Upstream port
Multiple Downstream ports (2 up to 32)
Independent configuration of link width, link speed, equalization settings, and PIPE interface per-PCIe port
PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
L1 and wake-up events forwarding
Peer-to-peer transactions support
Round-Robin arbitration
No Packet buffering
Test port functionality
User clock - integrated Clock Domain Crossing to support user-selected frequency in the Switching logic

PCI Express Interface

x1, x2, x4, x8 PCI Express Core
256-bit data path
Supports link rate of 2.5, 5.0, 8.0, 16 and 32 Gbps per lane
PCI Express Based Specification Revision 3.1 compliant
PHY Interface for PCI Express (PIPE) 3.0 rev.0/4.0/4.2 compliant
1 Virtual Channel (VC)
8-bit, 16-bit, 32-bit PIPE interface
Receive and Replay configurable buffer size
Advanced Error Reporting (AER) support
ECRC generation and check support
Cut-Through mode to reduce latency
Lane reversal

Customization

Easy IP customization
Unused features not implemented in silicon

Benefits

Flexibility: The solution is highly configurable and scalable. For example, the designer can choose to implement up to 32 external or embedded Endpoints, and define for each port a different clock speed, data rate and throughput in order to optimize the footprint of the design.
20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 5700 customers , including several hundred of ASIC tape-outs.
Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
Significant Latency, Power and Performance Improvements: XpressSWITCH delivers improvements in latency (using Cut-Through mode), optimization of power consumption (using embedded Endpoints), and better performance through a non-blocking architecture (using Peer-to-Peer transfers between Endpoints).
Demonstrated reliability: The solution has been integrated, tested and demonstrated on PLDA’s XpressKUS FPGA board running a Xilinx® Kintex® UltraScale™ device and has achieved PCI Express (PCIe®) compliance.
No requirement for software development: The switch will work without additional software development through the use of the configuration wizards and reference designs provided, reducing time-to-market
BOM/Cost savings: PCIe Embedded Switch IP enables a minimized footprint and reduces the number of chips required on the board.
Shorter time-to-market: PCIe Embedded Switch IP enables the reuse of existing design, reducing design time and creating independence from the SerDes Technology.

Block Diagram

Applications

HPC,
Cloud Computing,
AI,
Machine Learning,
Enterprise,
Networking,
Automotive,
AR/VR,
Test and Measurement

Deliverables

Verilog RTL,
Supporting Documentation

Technical Specifications

Foundry, Node

Any

Maturity

In production

Availability

Available

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