PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customization and complies with the PCIe2.0 standard specifications while incorporating mixed signal circuits to provide 2.5GT/s and 5.0GT/s data transfer speeds. Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS) are the two levels that make up the PCIe2.0 PHY IP. It simply connects to either the PCIe2.0 MAC layer utilizing the industry-standard PIPE-3.0 interface.
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and small die area while retaining great result and data throughput. The PCIe2.0 PHY IP includes an on-chip physical transceiver solution with ESD protection, a built-in self-test module with inbuilt jitter injection, and a dynamic normalization circuit that ensures full support for high-performance configurations.
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
Overview
Key Features
- Compatible with PCIe base Specification
- Full compatible with PIPE4.2 interface specification
- Independent channel power down control
- Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
- Support 16-bit/32bit parallel interface
- Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
- Support flexible reference clock frequency
- Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
- Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
- Support programmable transmit amplitude and Deemphasis
- Support TX detect RX function in PCIe Mode
- Support Beacon signal generation and detection in
- Production test support is optimized through high coverage at-speed BIST and loopback
- Integrated on-die termination resistors and IO Pads/Bumps
- Embedded Primary & Secondary ESD Protection
- ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
- Silicon Proven in SMIC 55LL/SP/EF
Block Diagram
Deliverables
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Technical Specifications
Foundry, Node
SMIC 55LL, SMIC55SP, SMI55EF
Maturity
In Production
Availability
Immediate
Related IPs
- PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 14SF+
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 28SF