PCI Express (PCIe) 5.0 Controller

Overview

Application-optimized, high-performance controller IP for PCIe

The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a root complex (RC), endpoint (EP), or dual mode (DM) controller into any system-on-chip (SoC). Compliant with PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications, the Controller IP has over 100 configuration features to customize the controller to the specific needs of any computing, networking, or storage application. The Controller IP is engineered to quickly and easily integrate into any SoC and connect seamlessly to a Cadence or thirdparty PIPE 5.x- or PIPE 4.4.1-compliant PHY. Client applications access the controller through an industry-standard Arm® AMBA® 3 or 4 AXI interface or through a native Cadence Host Adaptation Layer (HAL/HLS) interface.

Key Features

Compliant with PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
32/16b interface for 500MHz or 1GHz core operation
Modes supported: Root Complex, EndPoint, or Dual Mode
SR-IOV and multifurcation options
Support for up to 4K payload size and 256 functions
ECNs, Error Counters, ECRC, and end-to-end datapath parity support
Superscalar design for high throughput and low latency
Configured to your specific needs – efficient implementation with minimal gate count
Optimized for use with Cadence PHY

Applications

Automotive,
Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace,
Others

Deliverables

Clean, readable, synthesizable RTL Verilog files
Verification testbench example with integrated stimulus and monitors
Verification test-plan and reports
Register descriptions
Synthesis and STA scripts

Technical Specifications

Maturity

Silicon Proven

Request Info