Parallel PCRAM Memory Model

Overview

Parallel PCRAM Memory Model provides an smart way to verify the Parallel PCRAM component of a SOC or a ASIC. The SmartDV's Parallel PCRAM memory model is fully compliant with standard Parallel PCRAM Specification and provides the following features. Better than Denali Memory Models.

Parallel PCRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Parallel PCRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports Parallel PCRAM memory devices from all leading vendors.
Supports 100% of Parallel PCRAM protocol standard.
Supports all the Parallel PCRAM commands as per the specs.
Supports device density up to 128MB.
Supports Serial peripheral interface (SPI).
Supports high performance READ

115ns initial READ access
135ns initial READ access
25ns, 8-word asynchronous-page READ

Supports Phase change memory (PCM).
Supports Power transition ERASE/PROGRAM lockout.
Supports Individual zero-latency block locking.
Supports Individual block lock-down.
Checks for following

Check-points include power on, Initialization and power off rules
State based rules, Active Command rules
Read/Write Command rules etc.
All timing violations.

Quickly validates the implementation of the standard Parallel PCRAM specification.
Bus-accurate timing for min, max and typical values.
Constantly monitors Parallel PCRAM behavior during simulation.
Protocol checker fully compliant with Parallel PCRAM Specification.
Notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of Parallel PCRAM designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the Parallel PCRAM testcases.
Complete UVM/OVM sequence library for Parallel PCRAM controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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