OSU processor, optimized for E1/FE/GE services with Ethernet over SDH over OTU0/OTU1 lines

Overview

The TPS3215MP OSU processor is an IP Core solution designed for Xilinx FPGAs. TPS3215MP processors accept 4x FE/GE and 4x E1 client signals, process and present them to either SDH VC, OSU or ODU containers for their transport over OTU0/OTU1 bearers. TPS3215MP processors include an Ethernet-over-SDH (EoS) capability. The OTU line signals can be configured in 1+1 protection configurations, offering protection at the OTU/ODU/OSU/SDH levels. For Ethernet client-services, Ethernet rate-limiting is provided. TPS3215MP processors support hitless bandwidth adjustment of OSU containers carrying Ethernet information. Integrated HDLC controllers can be assigned to GCC in-band communications channels. TPS3215MP processors are offered as complete turn-key solutions for Xilinx FPGAs, including built-in jitter attenuators.

Key Features

Line Signals: 2x OTU0/1
Protection: 1+1 at the OTU/ODU/OSU/VC levels
Integrated HDLC controllers for GCC channels
Client Signals: 4x FE/GE and 4x E1
Built-In jitter attenuators for Line and Client signals
Mapping of client signals to OSU/ODU/VC transport containers
Alarms and Performance Counters for Client/Line signals.
Ethernet Rate-Limiting
Ethernet-over-SDH (EoS): FE/GE mapping to SDH Virtual Containers (VCs)
SDH: STM4 signal
Maintenance: Loopbacks, PRBS generation and monitors
Control: PCIe/Parallel

Benefits

Single-Chip (IP Core) solution for OSU-based OTN Remote Terminals (RT)
Optimizes line-side bandwidth thanks to SDH VC and OSU transport containers
Interoperability with legacy SDH infrastructure: Built-In Ethernet-over-SDH
Supports Tri-Mix capability for Ethernet client-signals: Mapping of FE/GE to SDH VC/OSU/ODU transport containers
Rate-Limiting for Ethernet client-services
Seamless integration with the existing G.709 OTN infrastructure

Block Diagram

Applications

OSU based remote terminals

Deliverables

Bin File with Security key

Technical Specifications

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