The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support both single-ended and differential ONFI 4.1 signaling. This library also meets the requirements for ONFI 3.0 & Toggle 2.0 signaling. Also included is a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated ONFI domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.
The ONFI 4.1 I/O library supports all impedance modes defined in the ONFI 4.1 specification and features fast and precise calibration, low power consumption, area-efficient design, and easy integration into the physical layer (PHY).
This 7nm library is available in a staggered flip chip implementation.
ESD Protection:
? JEDEC compliant
o 2KV ESD Human Body Model (HBM)
o 500 V ESD Charge Device Model (CDM)
Latch-up Immunity:
? JEDEC compliant
o Tested to I-Test criteria of ± 100mA @ 125°C
ONFI_4 IO Pad Set
Overview
Key Features
- ONFI Single-Ended Driver / Receiver Features:
- ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30? / 50? / 75? / 100? / 150?
- o ZOUT = 18? / 25? / 35? / 50?
- o Off state – Z / pull-up / pull-down / bus keeper
- ? Receiver – single-ended and pseudo-differential outputs
- ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
- ? Maximum operating frequency – 400 MHz
- ONFI Differential Clock Driver / Receiver Features:
- ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
- o ODT Rtt = 30? / 50? / 75? / 100? / 150?
- o ZOUT = 18? / 25? / 35? / 50?
- o Off state – Z / pull-up / pull-down / bus keeper
- ? Receiver – single-ended and true differential outputs
- ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
- ? Maximum operating frequency – 400 MHz
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSMC 7nm
Maturity
Silicon Proven
Availability
Available Now
TSMC
Pre-Silicon:
7nm