ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
Overview
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY
Key Features
- Support ONFi 4.1 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 up to 533Mbps
- Support NV-DDR3 up to 1200Mbps
- Per DQ (per bit) delay line for controlling skew
- SDLL is included for DQS/DQ phase tuning by DLY setting
- On die De-coupling capacitor (>1nF per channel) for Power Integrity to save PKG capacitor
- Operation temperature: -40 to 125 °C
- Flip-Chip
- Supported metal scheme:
- 1P9M_2Xa1Xd3Xe2Z
- 1P10M_2Xa1Xd4Xe2Z
Block Diagram
Technical Specifications
Foundry, Node
TSMC 12FFC
Maturity
In Production
Availability
Immediate
TSMC
In Production:
12nm
Related IPs
- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC