Vendor: T2M GmbH Category: Single-Protocol PHY

ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)

ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…

TSMC 12nm FFC In Production View all specifications

Overview

ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY

Key features

  • Support ONFi 4.1 IO Electrical Specification
  • Support Legacy up to 50MHz
  • Support NV-DDR2 up to 533Mbps
  • Support NV-DDR3 up to 1200Mbps
  • Per DQ (per bit) delay line for controlling skew
  • SDLL is included for DQS/DQ phase tuning by DLY setting
  • On die De-coupling capacitor (>1nF per channel) for Power Integrity to save PKG capacitor
  • Operation temperature: -40 to 125 °C
  • Flip-Chip
  • Supported metal scheme:
  • 1P9M_2Xa1Xd3Xe2Z
  • 1P10M_2Xa1Xd4Xe2Z

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC In Production

Specifications

Identity

Part Number
ONFI 4.1 PHY IP
Vendor
T2M GmbH

Provider

T2M GmbH
T2M GmbH is the leading Global Technology Company supplying state of the art complex semiconductor connectivity IPs and KGDs, enabling the creation of complex connected devices for Mobile, IoT and Wearable markets. T2M's unique SoC White Box IPs are the design database of mass production RF connectivity chips supporting standards including Wifi, BT, BLE, Zigbee, NFC, LTE, GSM, GNS. They are available in source code as well as KGD for SIP / modules. With offices in USA, Europe, China, Taiwan, South Korea, Japan, Singapore and India, T2M’s highly experienced team provides local support, accelerating product development and Time 2 Market.

Learn more about Single-Protocol PHY IP core

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Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

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Frequently asked questions about Single-Protocol PHY IP

What is ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)?

ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC) is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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