ONFI 4.1 I/O Pad Set

Overview

The ONFI 4.1 library provides the combo driver / receiver cells, the
ODT / driver impedance calibration cell, and the voltage reference
cell to support both single-ended and differential ONFI 4.1 signaling.
This library also meets the requirements for ONFI 3.0 & Toggle 2.0
signaling. The pad set includes a full complement of power, spacer,
and adapter cells to assemble a complete pad ring by abutment. An
included rail splitter allows isolated ONFI domains to be placed in
the same pad ring with other power domains while maintaining
continuous VDD/VSS in the pad ring for robust ESD protection. Ported from our TSMC 16 silicon proven design.


? ONFI 4.1 Single-Ended Driver /Receiver
? ONFI 4.1 Differential Clock Driver / Receiver
? ODT / ZO Calibration Cell
? Voltage Reference

Key Features

  • ONFI Single-Ended Driver / Receiver Features:
  • ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
  • o ODT Rtt = 30? / 50? / 75? / 100? / 150?
  • o ZOUT = 18? / 25? / 35? / 50?
  • o Off state – Z / pull-up / pull-down / bus keeper
  • ? Receiver – single-ended and pseudo-differential outputs
  • ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
  • ? Maximum operating frequency – 400 MHz
  • ONFI Differential Clock Driver / Receiver Features:
  • ? Driver – user-selectable on-die termination and programmable drive strength with ODT / ZO calibration and programmable “off” state control.
  • o ODT Rtt = 30? / 50? / 75? / 100? / 150?
  • o ZOUT = 18? / 25? / 35? / 50?
  • o Off state – Z / pull-up / pull-down / bus keeper
  • ? Receiver – single-ended and true differential outputs
  • ? Powered by 1.2V / 1.8V I/O and 0.8V core supplies
  • ? Maximum operating frequency – 400 MHz

Deliverables

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node
TSMC 12nm
Maturity
Silicon Proven
Availability
Available Now
TSMC
Pre-Silicon: 12nm
Silicon Proven: 12nm
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Semiconductor IP