The LOGAN - On-chip Logic Analyzer IP core can trace and display on-chip signals. When armed, the on-chip logic analyzers stores the traced signals in the circular buffer until a trigger condition occurs. A trigger condition will freeze the buffer, and the traced data can then be read out via an AMBA APB interface.
On-Chip Logic Analyzer
Overview
Key Features
- Compliant with the AMBA 2.0 specification
- Provides an AMBA APB interface for configuration and accessing the stored samples
- User-selectable trace signal count ranging from 1 to 255
- Trace buffer size user-selectable from 256 to 16384 samples
- Supports up to 63 separate triggering levels with individual patterns and masks
- Extensive and run-time programmable triggering conditions
- Supports user defined post-, center- or pre-triggering modes
- Programmable sample frequency divider
- Optional pipeline operation to support slow on-chip memory
- Fully synchronous operation
- Downloadable IP core and tools from the Gaisler Research web site
- Written in VHDL
- Compatible with FPGA and ASIC technologies
- Inserted during design capture
- Supports Gaisler Research GRLIB IP-library plug&play capabilities
- Compatible with the Gaisler Research GRMON debug monitor
- Controllable via graphical user interface (GUI) written in Tcl/Tk
- Compatible with VCD waveform file generation
- Compatible with GTKWave, Dinotrace, ModelSim, etc.
- Supports interfacing from any type of on-chip AMBA AHB master: e.g. processor, UART, JTAG, USB, Ethernet
Benefits
- Fully integrated with Gaisler Research GRLIB VHDL IP-library, providing a complete AMBA-based solution
- Compatible with the LEON3 32-bit SPARC processor
- Easy to instantiate and use
- High-speed trigger detection and sample
- Reduces the risk for design mistakes leading to silicon re-spin
- Can be used for analyzing any internal FPGA signal, including the AMBA busses
- Allows remote debugging via internet (using GRMON)
Deliverables
- VHDL source code
- Synplify project file
- Synthesis scripts
- User's manual
- Template design for LEON3 processor
- GRMON debug monitor (optional commercial product)
Technical Specifications
Maturity
Production
Availability
Now
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