App\Entity\TrafficIpAddress {#572
  -id: 37661
  -ipaddress: "216.73.216.142"
  -createdAt: DateTimeImmutable @1751574870 {#561
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -updateAt: DateTimeImmutable @1751888735 {#562
    date: 2025-07-07 11:45:35.0 UTC (+00:00)
  }
  -counter: 1
  -isBlacklisted: false
  -lastAccessAt: DateTimeImmutable @1751574870 {#563
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -isWhitelisted: false
  -counterFiveMinutes: 0
  -counterOneHour: 0
  -counterOneDay: 0
  -counterOneWeek: 0
  -counterTwoWeeks: 0
  -fiveMinutesCreatedAt: DateTimeImmutable @1751574870 {#564
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -oneHourCreatedAt: DateTimeImmutable @1751574870 {#565
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -oneDayCreatedAt: DateTimeImmutable @1751574870 {#566
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -oneWeekCreatedAt: DateTimeImmutable @1751574870 {#567
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -twoWeeksCreatedAt: DateTimeImmutable @1751574870 {#568
    date: 2025-07-03 20:34:30.0 UTC (+00:00)
  }
  -statusUpdatedAt: DateTimeImmutable @1751574901 {#569
    date: 2025-07-03 20:35:01.0 UTC (+00:00)
  }
  -isAuthorizedCrawler: true
  -crawlerName: "ClaudeBot"
  -host: "216.73.216.142"
  -userAgent: "Mozilla/5.0 AppleWebKit/537.36 (KHTML, like Gecko; compatible; ClaudeBot/1.0; +claudebot@anthropic.com)"
  -counterVisitorFullDescription: 1
  -counterVisitorFullDescriptionCreatedAt: DateTimeImmutable @1751888735 {#570
    date: 2025-07-07 11:45:35.0 UTC (+00:00)
  }
}
OCP Assertion IP IP
IP Catalog > DSP & Math IP > Building Blocks IP > Transform IP > FFT IP > OCP Assertion IP

OCP Assertion IP

Overview

OCP Assertion IP provides an efficient and smart way to verify the OCP designs quickly without a testbench. The SmartDV's OCP Assertion IP is fully compliant with standard OCP Specification.

OCP Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

OCP Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • OCP 2.0/2.1/2.2 support
    • All signal level checks including X detection
    • Support transaction and transfer level checks
    • Support for all data and address widths
    • Supports all OCP protocol burst models, burst lengths and response types
    • SRMD and MRMD bursts support
    • Request interleaving support
    • Supports 2-Dimensional block burst address sequences.
    • Compliance to phase-ordering rules.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV OCP VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure OCP Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

OCP Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Short description
OCP Assertion IP
Vendor
Vendor Name
Request Info

Related IPs

×
Semiconductor IP