nvSRAM Memory Model

Overview

nvSRAM Memory Model provides an smart way to verify the nvSRAM component of a SOC or a ASIC. The SmartDV's nvSRAM memory model is fully compliant with standard nvSRAM Specification and provides the following features. Better than Denali Memory Models.

nvSRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

nvSRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports nvSRAM memory devices from all leading vendors.
Supports 100% of nvSRAM protocol standard nvSRAM specification.
Supports all the nvSRAM commands as per the specs.
Quickly validates the implementation of the nvSRAM standard.
Supports up to 1MB memory density.
Supports for write protection.
Support the following devices.

Supports for RTC with watch dog timer and clock alarm with programmable interrupts.
Supports for hardware store, hardware recall, software store and software recall.
Supports for interrupt and flag register programming.
Supports for power down features.
Supports for SPI with 40-MHz and 104-MHz.
Supports for SPI mode 0 and mode 3.
Supports for SPI status register, read status register, fast read status register and write status register programming.
Supports for I2C with 100-kHz and 400-kHz speed and fast mode with1-MHz speed.
Supports Zero cycle delay reads and writes.
Supports Sleep mode operation.
Supports for RTC registers and control registers programming.
Supports for auto store inhibit modes.
Checks for following

Check-points include power up initialization and power off rules,
State based rules, Active Command rules,
Read/Write Command rules etc.
All timing violations.

Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Protocol checker fully compliant with nvSRAM Specification.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Constantly monitors nvSRAM behavior during simulation.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of nvSRAM designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the nvSRAM testcases.
Complete UVM/OVM sequence library for nvSRAM controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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