NVMe IP core -- Directly connect PCIe SSD without external memory
Overview
NVMe IP core operating with AXI PCIe Bridge IP from Xilinx is ideal to access NVMe PCIe SSD without CPU and external memory. It is recommended to use in the application which require high capacity storage at very high-speed performance. Small size system can be also designed by M.2 storage which uses PCIe protocol standard. The IP core license includes the reference design for Xilinx FPGA boards. It helps you to reduce development time and cost.
Key Features
- Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
- Simple user control I/F and FIFO interface for data port
- Direct connect to AXI Bridge for PCIe IP from Xilinx by using 128-bit bus interface
- Include 256 Kbyte RAM to be data buffer
- Support three commands, i.e. IDENTIFY, WRITE, and READ
- Supported NVMe device
- Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)
- MPSMIN (Memory Page Size Minimum): 0 (4Kbyte)
- MDTS (Maximum Data Transfer Size): 0 (no limitation) or at least 5 (128 Kbyte)
- Reference design with AB16-PCIeXOVR adapter board available on Xilinx FPGA boards
- Support PLDA PCIe IP
Block Diagram
Technical Specifications
Related IPs
- Direct Memory Access Controller IP Core
- I2C Controller IP – Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses or direct to/from Registers or Memory
- 3.3v to 2.5v with 30mA driving capability without external capacitor (Cap-less), use trimming PADs; Linear Regulator; UMC 40nm LP/RVT LowK Logic process
- 3.3V to 1.2V with 150mA driving capability without external capacitor(Cap-less); use trimming ports (need e-Fuse IP); Linear Regulator; UMC 55nm eFlash LowK Logic Process
- SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface
- Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode