NVMe IP core -- Directly connect PCIe SSD without external memory
Overview
NVMe IP core operating with AXI PCIe Bridge IP from Xilinx is ideal to access NVMe PCIe SSD without CPU and external memory. It is recommended to use in the application which require high capacity storage at very high-speed performance. Small size system can be also designed by M.2 storage which uses PCIe protocol standard. The IP core license includes the reference design for Xilinx FPGA boards. It helps you to reduce development time and cost.
Key Features
- Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
- Simple user control I/F and FIFO interface for data port
- Direct connect to AXI Bridge for PCIe IP from Xilinx by using 128-bit bus interface
- Include 256 Kbyte RAM to be data buffer
- Support three commands, i.e. IDENTIFY, WRITE, and READ
- Supported NVMe device
- Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)
- MPSMIN (Memory Page Size Minimum): 0 (4Kbyte)
- MDTS (Maximum Data Transfer Size): 0 (no limitation) or at least 5 (128 Kbyte)
- Reference design with AB16-PCIeXOVR adapter board available on Xilinx FPGA boards
- Support PLDA PCIe IP
Block Diagram
Technical Specifications
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