The Flash MX IP Core implements a hardware accelerator for zstd compression and decompression. Compute-intensive software-based compression is offloaded from the host to the IP, delivering high compression performance at unmatched power efficiency.
NVMe expansion
Overview
Key Features
- Turn key solution: compression, compaction, memory management
- Transparent addressing to operating system and applications
- Operates on page granularity to enable high compression performance
Benefits
- Standards
- Hardware accelerated zstd
- Compression algorithm: zstd
- Interface: AXI4, CHI
- Architecture
- Modular architecture, enables scalability to meet customer throughput requirements
- Architectural configuration parameters accessible to fine tune performance
Deliverables
- Performance evaluation license
- C++ compression model for integration in customer performance simulation model
- FPGA evaluation license
- Encrypted IP delivery (Xilinx)
- HDL Source Licenses
- Synthesizable System Verilog RTL (encrypted)
- Implementation constraints
- UVM testbench (self-checking)
- Vectors for testbench and expected results
- User Documentation
Technical Specifications
Maturity
Tape-out
Availability
Immediate
Related IPs
- Stallable 1toN Expansion Pipeline Register
- LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process
- High Performance NVMe for PCIe-based storage
- NVMe Target IP Core
- NVMe IP core -- Directly connect PCIe SSD without external memory
- NVMe Host Recorder on Mini-ITX Zynq 7