A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are a powerful family of FEC codes that allow for very low error rates, approaching the Shannon capacity limit.
While binary LDPC codes have shown great performance, nonbinary LDPC codes have empirically shown even better performance, especially for small codeword lengths.
A configurable output synchronous FIFO is used to store the output for the next block.
Nonbinary LDPC Decoder
Overview
Key Features
- Regular parity check matrix
- Soft decision SPA decoding
- Supports different code sizes
- Hard decision output
- Log-domain implementation
- Configurable number of decoding iterations
- Higher-order Galois field GF(2m)
Applications
- Real-time applications
- Short codeword length applications
- BeiDou Navigation Satellite System
Deliverables
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Test Benches
- Documentation
Technical Specifications
Maturity
In Production
Availability
Immediate