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NAND Flash Controller

Overview

Cadence IP Controller for ONFI NAND and Toggle NAND

NAND Flash memory is widely used for data storage in computers and multiple consumer and enterprise applications. It is the basic building block for SSD applications, as well as USB drives, SD cards, etc. NAND Flash requires special handling and management, including error detection and correction, and the Cadence® Controller IP for NAND Flash deals with those complexities, enabling our customers to create simple and quick systemon-chip (SoC) designs. The Controller IP for NAND Flash provides the logic required to support ONFi 4.0/4.1-compliant memory in any SoC. Supporting ONFI 4.x (excluding EZ-NAND), ONFI 3.x, ONFI 2.x., and Toggle Mode DDR-1/2 NAND Flash devices, the Controller IP for NAND Flash has many configurable features and input parameters to customize the controller for the specific needs of any application. The Controller IP for NAND Flash is architected to quickly and easilyintegrate into any SoC through the industry-standard Arm® AMBA® 4 AXI protocol as a high-speed master interface and the AMBA APB and AXI-Lite protocols as register interfaces. The Controller IP for NAND Flash is part of the comprehensive Cadence Design IP portfolio comprised of Interface, Memory, Analog, System, and Peripheral IP.

Key Features

  • Support for SLC, MLC, and TLC devices (in SLC mode), including for boot operation
  • Support for high-speed memories (up to 1200MT/s)
  • Support for all flash memory vendors
  • Supports pages sizes from 256B to 16kB
  • 8-bit and 16-bit flash device support
  • Advanced ECC supports different parallel factors to achieve maximum throughput
  • Command DMA supports 32-bit or 64-bit addressing
  • Pipelined read-ahead and write commands for enhanced read and write throughput
  • Silicon proven and shipping in volume
  • Support for multi-LUN modes

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

Deliverables

  • Clean, readable, synthesizable Verilog RTL
  • Verilog testbench with memory model and sample tests
  • Cadence Genus® Synthesis Solution scripts
  • Documentation—integration and user guide, release notes
  • Cadence NAND Driver as an optional deliverable

Technical Specifications

Maturity
Available on request
Request Info

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