IP Catalog > Security IP > Crypto Accelerator IP > Public Key Accelerator IP > Multipurpose Security Protocol Accelerator

Multipurpose Security Protocol Accelerator

Overview

Complex system-on-chip (SoC) requirements can include security at the MAC layer, VPN layer, and application layer. The SynopsysSecurity Protocol Accelerator (SPAcc) IP addresses these needs with support for the Wi-Fi, MACsec, IPsec, SSL/TLS/DTLS, and SRTP security standards. The SPAcc
IP offers high throughput with support for mixed packet size traffic and low latency to preserve quality of service in voice and video applications in single- and multi-core processor architectures. The product is a highly customer configurable enabling solution to be tuned for specific applications providing differentiation in the market.
The Synopsys SPAcc optionally includes the following cryptographic support:

• 3GPP/LTE/LTE-Advanced wireless security: ZUC, SNOW 3G and KASUMI algorithms
• Chinese security: SM3 and SM4 algorithms
• DPA/TA side channel countermeasures: for AES, SM4, DES/3DES algorithms

Benefits

  • Highly customer configurable, silicon- proven security accelerators
  • Support for cipher, hash and AEAD algorithms used in major security protocols using parallel hashing and encryption
  • AES, DES/3DES
  • SHA-3 hashing, HMAC, KMAC, cSHAKE, and XOF support
  • ChaCha20 cipher, Poly1305 hash and combined AEAD algorithm
  • Built-in scatter/gather DMA capability offloads the host processor
  • QoS and virtualization features
  • Secure Key Port to access confidential data stored in NVM
  • Configurable AMBA® AXI™ and AHB™ system bus interfaces, with TrustZone™ support
  • Optional: Wireless security algorithms ZUC, SNOW 3G and KASUMI; Chinese security algorithms SM3 and SM4; DPA/TA side channel countermeasures for AES, SM4, DES/3DES

Applications

  • Networking protocols (e.g. TLS, IPsec)
  • Wireless (3GPP, LTE, LTE-Advanced)
  • Internet of Things (IoT)
  • Mobile communications
  • Automotive
  • Content protection and digital rights management

Deliverables

  • Verilog HDL
  • Testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Documentation

Technical Specifications

Maturity
Available on request
Availability
Available
Request Info

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